1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and a semiconductor device provided with a contact pad and a contact plug respectively formed on a source and a drain of a metal oxide semiconductor field effect transistor (MOSFET) and adapted to bring the source and drain into contact with conduction layers, and a method for fabricating the semiconductor device.
2. Description of the Prior Art
For obtaining a semiconductor device with a higher integration degree, generally, patterns of the semiconductor device are formed to have minimum pattern spaces by a lithography process. In this case, however, the semiconductor device topology is inevitably increased.
Such an increased topology results in an increase in an aspect ratio of a contact hole subsequently formed to bring a conduction layer into contact with a semiconductor substrate of the semiconductor device. This causes problems of poor step coverage of the conduction layer being in contact with the semiconductor substrate and an increase in contact resistance.
In order to solve such problems, there have been proposed techniques of provision of a contact plug formed by burying the conduction layer in a lower portion of the contact hole and formation of a contact pad being in contact with the semiconductor substrate.
These conventional techniques will now be described in conjunction with FIG. 1 and FIGS. 2A to 2F.
FIG. 1 shows a layout of a MOSFET with a conventional contact structure. In FIG. 1, the MOSFET structure is shown in symmetry to its drain. As shown in FIG. 1, the MOSFET includes an active mask 50, a word line mask 52, a source/drain contact mask 54, a drain contact mask 56, a first conduction wiring mask 58 and a source contact mask 60.
FIGS. 2A to 2F are cross-sectional views respectively taken along the line X--X' of FIG. 1, showing a conventional method for forming contact plugs respectively on a source and a drain of the MOSFET structure shown in FIG. 1 and forming a conduction layer to come into contact with the contact plugs.
In accordance with this method, first, an insulating film 2 for an element isolation is formed on a predetermined portion of a semiconductor substrate 1, as shown in FIG. 2A. On the other portion of the semiconductor substrate 1, a MOSFET is then formed to include a gate oxide film 3, gate electrodes 4, a source 6 and a drain 6'. Thereafter, an insulating film 5 and insulating film spacers 7 are formed on the upper surface and side surfaces of each gate electrode 4, respectively. The insulating film 5 is comprised of an oxide film.
A thin oxide film 8 is then formed on the exposed source 6 and drain 6', as shown in FIG. 2B. Over the entire exposed surface of the resulting structure, a first insulating film 10 for planarization is formed. The first insulating film 10 is comprised of, for example, a borophosphosilicate glass (BPSG) film. Using a source/drain contact mask such as the mask 54 of FIG. 1, a formation of a photoresist film pattern 11 is then carried out.
Using the photoresist film pattern 11 as a mask, exposed portions of the first insulating film 10 are then subjected to an etch, as shown in FIG. 2C. Subsequently, the thin oxide film 8 exposed after the etching of the first insulating film 10 is anisotropically etched, thereby forming contact holes 19 through which the source 6 and the drain 6' are exposed, respectively. The contact holes 19 are formed in a self-aligned manner by virtue of the insulating spacers 7. Thereafter, the photoresist film pattern 11 is removed. Over the entire exposed surface of the resulting structure, a conduction layer 12 is formed to a sufficient thickness so that it is buried in the contact holes 19.
Subsequently, the conduction layer 12 is fully etched until the upper surface of the first insulating film 10 is exposed, as shown in FIG. 2D. As a result, the remaining portions of the conduction layer 12 form contact plugs 12' respectively buried in the contact holes 19.
Over the entire exposed surface of the resulting structure, a second insulating film 14 is then formed to a predetermined thickness, as shown in FIG. 2E. Thereafter, the second insulating film 14 is subjected to an etch process using the drain contact mask such as the mask 56 of FIG. 1 so that the contact plug 12' being in contact with the drain 6' is exposed. Over the entire exposed surface of the resulting structure, a first conduction layer is deposited. The first conduction layer is then subjected to an etch process using a first conduction wiring mask such as the mask 58 of FIG. 1, thereby forming a first conduction wiring 15. Since the second insulating film 14 has a small thickness, it is not short-circuited with the gate electrode 4 even at a misaligned state of the first conduction wiring mask.
A third insulating film 16 is then formed over the entire exposed surface of the resulting structure, as shown in FIG. 2F. Using the source contact mask such as the mask 60 of FIG. 1, the third insulating film 16 is then etched so as to expose the contact plug 12' being in contact with the source 6. Thereafter, formation of a second conduction wiring 17 is carried out. By referring to FIG. 2F, it can be found that the second insulating film 10 and the first insulating film 4 disposed on each gate electrode 5 have been partially etched at the step of etching the insulating film 16 due to the source contact mask misaligned to the right, thereby causing the second conduction wiring 17 to be short-circuited with the gate electrode 4.
In accordance with the conventional method, such an undesirable short circuit phenomenon may occur easily because of small alignment margins of masks respectively given upon forming the contact plugs on the source and drain and forming the conduction layer patterns being in contact with the contact plugs.
In order to prevent such short circuit phenomenons from occurring upon forming contacts on the source and drain, the design of a semiconductor device should be made, taking into consideration a printing registration and a variation in critical dimension occurring upon fabricating a contact mask, a misalignment tolerance, a lens distortion and a variation in critical dimension occurring upon forming a pattern on a wafer. However, this results in an increased area of the semiconductor device.